In parallel processing under the environment of a multi-CPU core having a plurality of central processing unit (CPU) cores or a multi-CPU having a plurality of CPUs (hereinafter CPU core and CPU are referred to as a CPU), a plurality of CPUs shares the same address space and executes a store instruction (write) and a load instruction (read) with respect to the same memory. In this case, a plurality of CPUs accesses the same memory address and writes data thereto. Due to this, exclusive processing which uses locks is known as a mechanism for mediating such accesses.
In exclusive processing which uses locks, in a period where a plurality of CPUs are executing respective threads, a CPU executes a lock acquisition operation before executing a write operation to a shared memory, executes a write operation when a lock is acquired, and after that, executes an operation of releasing the lock. In a locked state, since lock acquisition by another thread is inhibited, a write operation to the shared memory is performed exclusively, and coherency of data within a memory is maintained.
However, exclusive processing which uses locks is a burden for programmers and causes bugs. Thus, a transactional memory which performs exclusive processing instead of locks has been proposed.
In a transactional memory, a series of accesses to a shared memory is referred to as a transaction. In the transactional memory, when a thread of a certain CPU accesses a shared memory and a thread of another CPU also accesses the shared memory, conflict of accesses is checked. When an access conflict is detected, a plurality of conflicting threads aborts the executing transactions, returns to the state before the transactions were started and executes the transactions again.
The above matters are disclosed in JP2008-515055 and JP2012-509529.
Two types of transactional memories have been proposed, including a software transactional memory which implements a transactional memory with software and a hardware transactional memory which implements a transactional memory with hardware. A hardware transactional memory is advantageous in that it poses a lesser programming burden on programmers, but is not able to perform complex determination processes. Thus, only transactions of threads of a specific CPU may be repeatedly aborted, and consequently, deadlocks may occur.
When aborts occur repeatedly, the control is handed over to a software abort handler and processing using locks is performed. As a result, the performance of a transactional memory may deteriorate.